CMOS transistors are used to implement a variety of complex logical operations. Attempts have been made to improve the speed of CMOS circuits by integrating bipolar transistors into CMOS circuits. Specifically, emitter coupled logic has been used in CMOS circuits for high speed operations. Emitter coupled logic is usually implemented with differential gates responding to small current swings. In contrast, CMOS circuits operate on a rail-to-rail (low-to-high voltage) basis. Thus, attempts to integrate bipolar logic into CMOS circuits have resulted in extra delays as conversions are made from the CMOS rail-to-rail domain to the emitter coupled logic differential domain. The delays associated with the conversions essentially negate any speed advantages otherwise provided by the use of bipolar circuits.
Thus, it would be highly desirable to provide a CMOS circuit that exploits the speed advantages of bipolar logic, without imposing conversion overhead between the CMOS and bipolar domains.